1. Field of the Invention
The present invention relates to semiconductor integrated circuit (IC) assembly technology, and more particularly, to a system for integrally managing data required for an automated wire bonding process.
2. Description of the Related Art
The assembly technology used for packaging and interconnecting electronic components is becoming a highly important field that affects the efficiency of computers or other kinds of electronic systems. A semiconductor chip package assists a semiconductor IC chip to be settled in the electronic system, and provides proper surroundings to guarantee good reliability and suitable operation of the IC chip. The package also electrically connects the IC chip with the electronic system.
With conventional plastic packages, a detailed description of the package assembly process is given below. The package assembly process begins with a wafer in which a great number of circuitries are already formed through the wafer fabrication process. The wafer is subjected to an electric die sorting (EDS) test. Depending on the result of the EDS test, failed dies (i.e., poor IC chips) in the wafer are marked with ink. The wafer is then sawed and divided into individual IC chips. A passed die (i.e., good IC chip) is bonded to one portion of a package base, for example, a die pad of a lead frame. This die bonding process typically; includes a step of coating adhesive material such as silver-poxy onto the package base, a step of placing the IC chip on the package base and a step of curing adhesive material. Thereafter, wires electrically connect the IC chip with another portion of the package base, for example, leads of the lead frame. Tape automated bonding or flip chip bonding can be alternatively used for such electrical connection. The IC chip and the package base are encapsulated in a plastic body by molding. Outer ends of the leads are bent into a suitable form, and a product number, etc. is marked on the plastic body. The finished package is then subjected to tests in reliability and electrical properties.
In the package assembly process, the wire bonding technology is most widely used for electrical interconnection between the IC chip and the lead frame. The wire bonding process should attain high throughput and economical production yield. For this reason, a high-speed wire bonder having a handling system and an image sensing system is generally employed. The handling system supplies the lead frame to a worktable, and the image sensing system permits the IC chip to coincide with a bonding diagram. An automatic thermosonic bonding is a high yield interconnection process that uses heat and ultrasonic energy to form a metallurgical bond. Typically, a gold wire is used and a ball bond is formed at one end and a stitch bond at the other. A ball is formed on the tail of the wire which extends from the end of a capillary. A hydrogen flame or an electronic spark may be used to form the ball. The capillary descends and presses down the ball onto an electrode pad of the IC chip while ultrasonic vibration is applied. After the ball is bonded to the IC chip, the wire forms a loop by sequential actions of the capillary. Then, the capillary deforms the wire against the lead of the lead frame, producing a wedge-shaped bond. The cycle is completed and ready for the next ball bond.
As described above, the wire connects the electrode pads and the leads one by one. Therefore, the high-speed wire bonding process requires information on both a chip layout and a lead frame structure. Further, there is a need for integrated management of both chip layout data and lead frame design data.
In order to enhance the production yield of the package assembly process, especially the wire bonding process, a good design rule of the IC chip should be primarily established and observed. The design rule has to accord with a specific type of the package to be manufactured and should be fitted to current assembly equipments. Further, it is desirable that the determination of the design rule is made before chip laying-out. As the size of the IC chip is reduced and the number of input/output pins is increased, an area necessary for electrical connection influences a chip size. In other words, reductions are required in electrode pad size, pad pitch, process tolerance, etc. Moreover, the chip layout directly influences automation and reliability of the assembly process. It is therefore preferable to incorporate the design rule into a chip layout CAD (computer aided design) system. For example, a wire bonding template that indicates ball bond and stitch bond positions based on the design rule is preferably used for the plastic package assembly process. By overlapping the template and the chip layout, a design engineer can determine desirable positions of the electrode pads.
For automation of the assembly process, it is also essential to apply data in each assembly step to subsequent assembly steps without additional modification or processing. A related technique is disclosed in U.S. Pat. No. 6,256,549 issued to Cirrus Logic, Inc. Herein, a computerized database includes a table representing a list of part numbers. The database provides computerized links between individual part numbers and associated manufacturing process data for different process steps or that part number. Rather than correlate data by hand, a user may click on a process step for a particular part number to instantly and accurately retrieve that data. Manufacturing process data may include wafer back-lapping process data, wire bonding data, testing parameters, packaging data, and marking data.
Another technique related to assembly automation is disclosed in U.S. Pat. No. 5,608,638 issued to Advanced Micro Devices. Herein, a system and method including a user interface for automation of a build sheet is provided. The database icon or command of the user interface is executed to select an appropriate package for an IC chip, and a blank bond master is downloaded to the hard disk of the workstation. The engineer can choose either the suggest die icon/command or the die cleaner icon/command to create an image file of the die pad ring based on a mask layer best representative of the die pad ring. Thereafter, the die pads and bond fingers are, identified and a net list is complied when the wire bonding icon or command is executed to create a bonding device diagram without the die image. A die image is created based on a mask layer best representative of the die using either the TIF to AutoCAD icon/command or the GDS to AutoCAD icon/command. The Die Image Merge icon/command merges the die image with the bonding device diagram to complete the build sheet. Thereafter, an IC package may be fabricated based on the bonding device diagram.
Though such conventional automation techniques may be helpful to an engineer who makes a bonding diagram for the automated wire bonding process, a design or product engineer engaged in mass production line for packaging numerous kinds of IC chips still needs much more improved automation technique. Additionally, a chip layout designer and a lead frame designer seldom benefit by conventional automation techniques. Further, if there is no particular platform, e.g., UNIX workstations, adapted for conventional techniques, an engineer or a designer has difficulty in using the automation techniques. Further, additional manual work is needed to utilize design data or assembly data, created by a CAD drawing tool operating at existing workstation platforms, as Assembly Reference or Bonding Specification at actual mass-production lines. Unfortunately, this requires excessive manual labor and time consumption, and may cause unexpected human error.